This invention relates to a low power redundancy circuit for a memory device for reducing power consumption in the redundancy circuit by using an evaluation signal of short pulse width and a latch-back MOSFET.
The prior arts regarding such redundancy circuit are illustrated in FIG. 1 through FIG. 3. FIG. 1 shows an address suppression redundancy circuit having a fuse circuit 1 which comprises fuses 6 to 13 and an address gate circuit 14 to 25 connected or disconnected by the fuses 6 to 13, and a dynamic-fused NOR gate circuit 3 and 4 inputting a control signal (.phi.EN).
If a column address is three (0011 in binary bit) and the column address is operated erroneously, the inputs of the address lines A3,A2,A1 and A0 should be in a high state and the fuses 6,8,11, and 13 in the fuse circuit 1 are disconnected. In this manner, the erroneous address is replaced.
In READ/WRITE operation of FIG. 2, if the column address of three is inputted and a time section is t&lt;TO,(that is in a stand-by state,) the input signal (.phi.EN) is in a high state (Vdd), and MOSFET 4 is in an "ON" state, and then an output(SPARE) 5 to a redundancy column decoder 2 is in a low state(ground).
If the input signal(.phi.EN) is changed to a low state at t=TO, MOSFET 4 turns "OFF" and MOSFET 3 turns "ON", and N channel MOSFET's 15,17,18, and 20 all turn "OFF", and then the output(SPARE) 5 is changed to a high state since MOSFET's 6,8,11, and 13 are here ruled out by the above fuses disconnection.
The output (SPARE) 5 operates the redundancy column decoder 2, or cuts off its operation. Since the column decoder including the erroneous column address is excluded by the logic operation of the redundancy circuit, it is not necessary to separate the erroneous column part from a word line driver of the column decoder.
But if the replaced column address is not inputted or the other column address is inputted, at least one N channel MOSFET turns "ON", a current induced through MOSFET 3 from the power Vdd flows to the ground through the N channel MOSFET of the fuse circuit 1 and the output(SPARE) 5 needs time to be changed to a high state. Accordingly, the prior art method also has a problem consuming more power.
FIG. 3 shows another prior art redundancy circuit for improving the prior art's problem.
In this redundancy circuit, an operation control fuse circuit 33 is composed of three MOSFET's 39 through 41 and a fuse 42. The fuse 42 performs a function to connect the power, VDD, and the output node of the operation control fuse circuit 33 if the fuse is not disconnected. Since two inputs to the OR gate 34 maintain a high state by the output (MASTER) 37 of the operation control fuse circuit 33 without respect to the other input (.phi.EN) in all time sections(t), MOSFET 35 always becomes "OFF" and MOSFET 36 always becomes "ON". Accordingly, this doesn't cause power consumption related with this operation.
But in using the redundancy circuit, if the fuse 42 is disconnected, this is the same as the circuit of FIG. 1. That is, if a particular column address is replaced, when TO.ltoreq.t&lt;T1, MOSFET 35 and the particular N channel MOSFET 36 turns "ON" in inputting this programmed column address and other normal column addresses. And then in this state, unnecessary power consumption still exists.